1. Field of the Invention
The present invention relates to sampling phase lock loops, in a particular, to control circuitry for sampling phase lock loops for reducing power consumption and spurious output signals.
2. Related Art
Referring to FIG. 1, a conventional phase lock loop (PLL) 10 includes a sampling phase detector 12, followed by a charge pump 14, a low pass filter 16 and a controllable signal source 18, typically a voltage controlled oscillator (VCO). An external reference signal source 20, often in the form of a crystal oscillator, provides a reference signal 21 which is buffered by a buffer amplifier 22 to convert the sine wave input signal 21 to a square wave reference signal 23. In accordance with this buffered reference signal 23, the sampling phase detector 12 samples the VCO output signal 19. The sampled signal 13 drives the charge pump 14, the output of which is filtered by the low pass filter 16 to produce the DC control signal 17 for the VCO 18.
Referring to FIG. 2, the reference buffer circuit 22 is often implemented as an inverter circuit 22a (or multiple such inverters 22a connected in series). In accordance with well known principles, during positive extremes of the input signal 21, the NMOS transistor 30n is turned on and the PMOS transistor 30p is turned off. Conversely, during negative extremes of the input signal, the PMOS transistor 30p is turned on and the NMOS transistor 30n is turned off. This produces the output square wave signal 23 having negative and positive signal excursions, respectively. However, between such positive and negative signal extremes, both transistors 30p, 30n will be conductive.
Referring to FIG. 3, this implementation 22a of the buffer circuitry 22 draws a significant amount of current from the power supply VDD. In order to achieve low PLL output signal 19 jitter, large transistor sizes are required for low reference clock signal noise. Accordingly, the large transistors 30p, 30n required for the inverting buffer circuit 22a can dominate the power consumption of the overall sampling PLL circuitry. As seen in the Figure, when the input sine wave voltage 21 is higher than the NMOS transistor 30n threshold voltage Vth,N, the NMOS transistor 30n is conducting. When the input voltage 21 is lower than the power supply voltage VDD minus the PMOS transistor 30p threshold voltage VDD-Vth,P, the PMOS transistor 30p is conducting. Since the power supply voltage VDD is typically larger than the sum of the threshold voltages, there will be a time interval when both the NMOS 30n and PMOS 30p transistors are conducting. This results in a direct path current that flows from the power supply VDD to circuit ground GND. This direct path current is not fundamentally required for a circuit operation, and is, therefore, a waste of power. In some cases such direct path current can account for more than 90% of the total power for the inverter circuit 22a. 
Referring to FIG. 4, the sampling circuitry 12 (FIG. 1) is typically implemented as a sampler circuit 12a having a series switch 40 and shunt capacitance 42. The switch 40 is opened and closed in accordance with the mutually opposed signal states of the square wave reference signal 23. This produces the sampled voltage 13 which is stored on the shunt capacitance 42 during the time intervals that the switch 40 is opened.
Referring to FIG. 5, the switching activity of such a sampler 12a tends to disturb operation of the VCO 18, thereby producing spurious output signals within the VCO output signal 19.
Referring to FIG. 6, in accordance with well known principles, differential circuitry can also be used as part of the PLL circuit 10. In such an implementation, the VCO 18d produces a differential output signal having mutually opposed positive 19p and negative 19n signal phases which are separately sampled by switches 40p, 40n controlled by the preferred reference signal 23, and stored on sampling capacitances 42p, 42n to produce positive 13p and negative 13n phases of a differential sampled signal voltage.
As noted above, the switch 40 (FIG. 4) is closed when the reference signal 23 is asserted (e.g., high) and open when the reference signal 23 is de-asserted (e.g., low). The sampling edge 23s is aligned in phase to a rising edge of the output signal 19. When the switch 40 is turned off, the sampled output voltage 13 is well defined and equal to the DC component of the VCO output voltage 19. This also means that when the switch 40 is turned on again the voltage 13 on the sampling capacitance 42 will be equal to this DC voltage component. However, the VCO voltage 19 at the moment that the switch 40 is turned on may not be equal to its DC component. This results in charge sharing between the output of the VCO 18 and the capacitance 42 in the sampler 12a. 
In other words, the switching activity of the sampler 12a periodically changes the loading of the output of the VCO 18. During the on time of the switch 40, the VCO output is loaded by the sampling capacitance 42, while during the off time of the switch 40, the VCO is disconnected and not loaded by the sampling capacitance 42. This change in loading produces changes in the frequency of the VCO output signal 19. The switch 40 is often implemented with a MOS transistor operating in its triode region. When the transistor is turned on or off, the channel charge within the MOS transistor is built or released and absorbed from or injected into, respectively, the output of the VCO 18. This results in spurious output signals being generated within the VCO output signal 19. In radio receiver applications, such spurious signals mixes undesirably in the channel bandwidth, thereby degrading the signal-to-noise ratio (SNR), and in clock data recovery applications, such spurious signals translate to peak-to-peak jitter, thereby increasing the bit error rate (BER).
Accordingly, it would be desirable to provide better control of a sampling PLL such that power supply consumption is reduced and spurious output signals are minimized.